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[VHDL-FPGA-Verilog] vhdlsynth_fft

Description: FFT的VHDL源代码的实现与仿真结果，经过FPGA源型机验证，已通过-FFT VHDL source code and the realization of simulation results, after FPGA source aircraft certification, have passed
Platform: | Size: 62464 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152576 | Author: 冯申 | Hits:

[VHDL-FPGA-Verilog] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[Post-TeleCom sofeware systems] VHDL_FIR

Description: 个人认为比较使用的几个VHDL源码之三FIR的源码-personally think that the use of the relatively few VHDL source of the ter FIR FOSS
Platform: | Size: 8192 | Author: xingqiba | Hits:

[VHDL-FPGA-Verilog] FIR_vhdl

Description: 基本FIR滤波器的VHDL源代码及其测试程序。-basic FIR filter VHDL source code and testing procedures.
Platform: | Size: 1024 | Author: qjyong | Hits:

[VHDL-FPGA-Verilog] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112640 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] FIR_beh

Description: FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
Platform: | Size: 1024 | Author: 郭兴波 | Hits:

[Communication-Mobile] VHDL_FIR11

Description: 用VHDL实现查找表方式的FIR滤波器-using VHDL search forms for the FIR filter
Platform: | Size: 11264 | Author: 梁立林 | Hits:

[VHDL-FPGA-Verilog] autofir

Description: 自适应滤波器设计的仿真程序，完全用C语言编写，可以作为滤波器设计的参考。原为VHDL实验要求的程序。-adaptive filter design simulation program, complete with C language can be used as filter design reference. VHDL to the original requirements of the experimental procedures.
Platform: | Size: 70656 | Author: 李博宁 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 此文件包括FIR滤波器的设计对EDA的介绍，以及用VHDL语言实现FIR滤波器的FPGA实现-This document includes the design of FIR filters on the EDA
Platform: | Size: 2531328 | Author: solor1985 | Hits:

[VHDL-FPGA-Verilog] New_HighSpeed_FIR_S_P

Description: 新型串并架构的高速FIR滤波器,对研究VHDL实现FIR的朋友有用处-New type of string and structure of high-speed FIR filters, the study of VHDL friends realize FIR has useful
Platform: | Size: 12288 | Author: 磊 | Hits:

[Communication-Mobile] FirGen_V1.1

Description: 產生你所需要的FIR濾波器，可以產生VHDL格式之源碼。-Have you need FIR filter, can generate VHDL source code format.
Platform: | Size: 368640 | Author: hcjian | Hits:

[DSP program] FIR

Description: 用DSP BUILDER设计的3阶和四阶滤波器-DSP BUILDER designed with 3-order and fourth-order filter
Platform: | Size: 18432 | Author: gillyamylee | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[VHDL-FPGA-Verilog] DecimationFilterDesignforDDCandImplementingItwithF

Description: 本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性-This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design
Platform: | Size: 468992 | Author: 会飞的鱼 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 里面是一个FIR滤波器的设计报告 里面有具体的 代码 等等 加法器 乘法器 见发起 等等 承平-There is a FIR filter design report there are specific code adder multiplier, etc., etc., see Cheng-Ping initiated
Platform: | Size: 189440 | Author: 丛宇 | Hits:

[MacOS develop] firVerilog

Description: 里面是一个FIR滤波器的VHDL语言 具体的功能里面有详细的介绍 对毕业设计者很有帮助的 -There is a FIR filter VHDL language specific features which are detailed introduction to the graduate designers helpful
Platform: | Size: 4096 | Author: 丛宇 | Hits:

[Communication-Mobile] suAra6Rm

Description: fir滤波器的Verilog程序,看看吧，还不错！-fir filter Verilog procedures, take a look at it, but also good!
Platform: | Size: 4096 | Author: wanghua | Hits:

[VHDL-FPGA-Verilog] firOK

Description: 17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真-17FIR 瞬 VHDL 爰?说 牡 苑
Platform: | Size: 1029120 | Author: fangyingjie | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实用VHDL教程,书中内容包括:了解数字集成电路的结构特点 掌握常用EDA工具的基本使用方法 掌握VHDL的基本语法和主要编程要点 掌握常用数字单元电路的VHDL设计 了解数字集成系统的基本设计方法-VHDL Tutorial practical book include: understanding the structural characteristics of digital integrated circuits commonly used EDA tools to master the basic use of VHDL to master basic grammar and the main programming elements commonly used to master the digital unit of VHDL circuit design of digital integrated system to understand the basic design method
Platform: | Size: 3379200 | Author: ff | Hits:
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